Analysis & Synthesis report for fibonacci2
Tue Aug  4 17:19:25 2020
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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and other software and tools, and any partner logic 
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(including device programming or simulation files), and any 
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Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                              ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Aug  4 17:19:25 2020       ;
; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name               ; fibonacci2                                  ;
; Top-level Entity Name       ; fibonacci2                                  ;
; Family                      ; MAX II                                      ;
; Total logic elements        ; 43                                          ;
; Total pins                  ; 25                                          ;
; Total virtual pins          ; 0                                           ;
; UFM blocks                  ; 0 / 1 ( 0 % )                               ;
+-----------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                              ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option                                                           ; Setting            ; Default Value      ;
+------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                            ; fibonacci2         ; fibonacci2         ;
; Family name                                                      ; MAX II             ; Cyclone V          ;
; Use smart compilation                                            ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                      ; Off                ; Off                ;
; Restructure Multiplexers                                         ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
; Preserve fewer node names                                        ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                         ; Auto               ; Auto               ;
; Safe State Machine                                               ; Off                ; Off                ;
; Extract Verilog State Machines                                   ; On                 ; On                 ;
; Extract VHDL State Machines                                      ; On                 ; On                 ;
; Ignore Verilog initial constructs                                ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
; Parallel Synthesis                                               ; On                 ; On                 ;
; NOT Gate Push-Back                                               ; On                 ; On                 ;
; Power-Up Don't Care                                              ; On                 ; On                 ;
; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
; Remove Duplicate Registers                                       ; On                 ; On                 ;
; Ignore CARRY Buffers                                             ; Off                ; Off                ;
; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore LCELL Buffers                                             ; Off                ; Off                ;
; Ignore SOFT Buffers                                              ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
; Optimization Technique                                           ; Balanced           ; Balanced           ;
; Carry Chain Length                                               ; 70                 ; 70                 ;
; Auto Carry Chains                                                ; On                 ; On                 ;
; Auto Open-Drain Pins                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
; Allow Synchronous Control Signals                                ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
; Auto Resource Sharing                                            ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
; Report Parameter Settings                                        ; On                 ; On                 ;
; Report Source Assignments                                        ; On                 ; On                 ;
; Report Connectivity Checks                                       ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
; Clock MUX Protection                                             ; On                 ; On                 ;
; Block Design Naming                                              ; Auto               ; Auto               ;
; Synthesis Effort                                                 ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
+------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                    ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                ; Library ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
; fibonacci2.sv                    ; yes             ; User SystemVerilog HDL File  ; /home/siddhant/intelFPGA_lite/19.1/fibonacci2/fibonacci2.sv ;         ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 43    ;
;     -- Combinational with no register       ; 5     ;
;     -- Register only                        ; 1     ;
;     -- Combinational with a register        ; 37    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 2     ;
;     -- 3 input functions                    ; 16    ;
;     -- 2 input functions                    ; 22    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 24    ;
;     -- arithmetic mode                      ; 19    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 21    ;
;     -- asynchronous clear/load mode         ; 6     ;
;                                             ;       ;
; Total registers                             ; 38    ;
; Total logic cells in carry chains           ; 21    ;
; I/O pins                                    ; 25    ;
; Maximum fan-out node                        ; state ;
; Maximum fan-out                             ; 39    ;
; Total fan-out                               ; 241   ;
; Average fan-out                             ; 3.54  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |fibonacci2                ; 43 (43)     ; 38           ; 0          ; 25   ; 0            ; 5 (5)        ; 1 (1)             ; 37 (37)          ; 21 (21)         ; 0 (0)      ; |fibonacci2         ; fibonacci2  ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 38    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 21    ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 37    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |fibonacci2|R0[11]         ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |fibonacci2|count[0]       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
    Info: Processing started: Tue Aug  4 17:19:01 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fibonacci2 -c fibonacci2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file fibonacci2.sv
    Info (12023): Found entity 1: fibonacci2 File: /home/siddhant/intelFPGA_lite/19.1/fibonacci2/fibonacci2.sv Line: 1
Info (12127): Elaborating entity "fibonacci2" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at fibonacci2.sv(32): truncated value with size 32 to match size of target (5) File: /home/siddhant/intelFPGA_lite/19.1/fibonacci2/fibonacci2.sv Line: 32
Info (21057): Implemented 68 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 8 input pins
    Info (21059): Implemented 17 output pins
    Info (21061): Implemented 43 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 870 megabytes
    Info: Processing ended: Tue Aug  4 17:19:25 2020
    Info: Elapsed time: 00:00:24
    Info: Total CPU time (on all processors): 00:01:00


